The present invention relates generally to an integrated logic circuit on a semiconductor chip and a design method therefor, and particularly, to an integrated logic circuit as a functional circuit composed of a set of various logic circuits (hereafter "combinational logic") and a set of clock-driven flip-flops (hereafter "FFs") combined therewith to exhibit a desired combinational function, in which selected ones of the FFs, smaller in number than a total thereof, are adapted for a serial connection therebetween to constitute a partial (not full) scan path circuit in a test mode of the integrated logic circuit, and to a partial scan path design method for designing a partial scan path circuit on the way to design an integrated logic circuit, where the integrated logic circuit has an arrangement of FFs therein designed as an object circuit of the design method, with necessary functional and clock connections therefor.